Job Title: Senior Static Timing Methodology Engineer
Salary Package: ₹25,000 – ₹45,000 a Month
Company Name: Google
Job Location: Bangalore, Karnataka
Qualification : Bachelor’s Degree
Job Info:
- Our computational challenges are so big, complex and unique we can’t just purchase off-the-shelf hardware, we’ve got to make it ourselves. Your team designs and builds the hardware, software and networking technologies that power all of Google’s services. As a Hardware Engineer, you design and build the systems that are the heart of the world’s largest and most powerful computing infrastructure. You develop from the lowest levels of circuit design to large system design and see those systems all the way through to high volume manufacturing. Your work has the potential to shape the machinery that goes into our cutting-edge data centers affecting millions of Google users.
Minimum qualifications:
- Bachelor’s degree in Electrical Engineering or Computer Science or equivalent practical experience.
- 5 years of experience in silicon timing closure and chip integration.
- Experience in one or more static timing tools (e.g., PrimeTime, Tempus).
- Experience with static timing analysis signoff constraints authoring for full-chip/subsystem level, tapeout signoff requirements, checklists and associated automation.
Preferred qualifications:
- Experience in the delivery of high complexity silicon in technology process nodes.
- Experience in engineering across timing analysis, physical design and high level implementation.
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Experience in extraction of design parameters, Quality of Results (QoR) metrics and analyzing data trends.
- Knowledge of semiconductor device physics and transistor characteristics.
- Knowledge of physical design/PnR implementation of complex blocks/subsystems/System on a Chip.
Responsibilities
- Define static timing analysis methodology through various margining techniques.
- Define reliability effects and account for reliability in timing signoff.
- Codify best known methods and model accuracy (libraries, IPs, SPICE models, etc.).
- Lead silicon correlation studies and data analysis.
- Align to signoff methodology recommendations and robust clock tree implementation strategies.